Lithographic method of manufacturing a device

ABSTRACT

For lithographically manufacturing a device with a very high density, a design mask pattern ( 120 ) is distributed on a number of sub-patterns ( 120   a,    120   b,    120   c ) by means of a new method. The sub-patterns do not comprise “forbidden” structures ( 135 ) and can be transferred by conventional apparatus to a substrate layer to be patterned. For the transfer, a new stack of layers is used, which comprise a pair of a processing layer ( 22; 26 ) and an inorganic anti-reflection layer ( 24; 28 ) for each sub-pattern. After a first processing layer ( 26 ) has been patterned with a first sub-pattern, it is coated with a new resist layer ( 30 ) which is exposed with a second sub-pattern, and a second processing layer ( 22 ) under the first processing layer is processed with the second sub-pattern.

The invention relates to a method of manufacturing a device in at leastone layer of a substrate, the method comprising the steps of:

-   -   providing a design pattern comprising pattern features        corresponding to device features to be configured in said layer;    -   transferring the design pattern in a resist layer provided on        said substrate layer;    -   removing material from or adding material to areas of said        layer, which areas are delineated by the patterned resist layer;    -   a number of sub-patterns each comprising different portions of        the design pattern being successively transferred in a        corresponding number of resist layers, which are successively        coated on said substrate layer.

The invention also relates to a method of distributing pattern featuresof a design pattern on a number of sub-patterns.

The invention further relates to an assembly of lithographic sub-maskstogether forming a fictitious design mask for configuring a devicepattern in a layer of a substrate.

For performing said manufacturing method, use is made of an opticallithographic projection apparatus. A lithographic projection apparatusis an essential tool in the manufacture of integrated circuits (ICs) bymeans of masking, etching and implantation techniques. For each devicelayer to be configured, a design mask pattern comprising patternfeatures corresponding to the device feature of said layer is imaged bymeans of such an apparatus in a radiation-sensitive film coated on saidlayer before the imaging step is performed. The design mask pattern isthe result of a pattern design process for a substrate layer, whichprocess precedes the substrate layer configuring process. Theradiation-sensitive layer, which is specifically sensitive to theradiation used for imaging, changes its properties in areas where theradiation is incident. Such a layer is an embodiment of a resist layer,which term also covers a layer which is sensitive to a charged-particlebeam, for example an electron beam. In practice, a radiation-sensitivelayer may also be sensitive to an electron beam. Transferring a patternis understood to mean both imaging a corresponding mask pattern in aresist layer and writing a pattern in such a layer, for example by meansof an electron beam. During the device manufacturing process,consecutive mask patterns, each one for another substrate layer, areimaged on the same target, for example IC area, on the substrate.

The lithographic method and apparatus may also be used in themanufacture of other devices like, for example, integrated or planaroptical devices, magnetic heads or liquid crystalline display panels.

A substrate is understood to mean a plate of material, for examplesilicon, into which a complete multilevel device, such as an IC, is tobe formed level by level by means of a number of successive sets ofprocessing steps. Each of these sets comprises as main processing steps:coating a radiation-sensitive, or resist, layer on the substrate,aligning the substrate with a mask, imaging the pattern of this mask inthe resist film, developing the resist film, etching the substrate viathe resist film, and further cleaning and other processing steps. Theterm substrate covers substrates at different stages in themanufacturing process, i.e. both a substrate having none or only onelevel of already configured device features and a substrate having allbut one level of already configured device features, and allintermediate substrates.

Since it is desirable to steadily increase the number of electroniccomponents in an IC device and the operating speed of such a device, thewidth of the device features, or line width, and the distance betweenthese features should be steadily decreased. As a consequence, maskpatterns with increasingly smaller pattern features and smallerdistances between these features should be imaged. The minimum size ofpattern features, which can be imaged with the required quality by alithographic projection apparatus, depends on the resolving power, orresolution, of the projection system of this apparatus and the structureof the mask pattern. This resolution is proportional to λ/NA, wherein λis the wavelength of the projection beam and NA is the numericalaperture of the projection system. An increase of the numerical apertureand/or a decrease of the wavelength could increase the resolution. Inpractice, an increase of the numerical aperture, which is fairly largein current lithographic projection apparatus, is not very well possiblebecause this reduces the depth of focus of the projection system, whichis proportional to λ/NA². Moreover, it becomes too difficult to correctthe projection system throughout the required image field when furtherincreasing the numerical aperture. A reduction of the wavelength in thedeep UV (DUV) region from 193 nm, as used in lithographic projectionapparatus nowadays under development, to, for example 157 nm poses newproblems with respect to materials for optical elements of theprojection system and resist films which are sensitive to the wavelengthof this radiation. It has been proposed for the next generation oflithographic projection apparatus to use extreme UW (EUV) radiation witha wavelength of the order of 13 nm. It is true that the use of suchradiation allows a considerably finer pattern structure to be imaged,but the design and development of an EUV projection apparatus is a verychallenging and time-consuming task. As EUV radiation is easily absorbedby air, the path of the projection beam should be in vacuum, which posesspecific and new problems. A suitable and efficient EUV radiation sourceis not available and also new resist materials, sensitive to EUVradiation, have to be developed. An EUV projection apparatus suitablefor device production will not become available in the coming years.

There is thus a great need for a method of manufacturing a device withdevice features which are considerably smaller as compared with those ofcurrently manufactured devices, which method uses a conventionalprojection apparatus.

U.S. Pat. No. 5,716,758 discloses a method of forming a fine periodiclinear pattern on a semiconductor substrate, which period is smallerthan the resolving power of the projection apparatus. In accordance withthis method, a first and a second chrome mask are formed, whose maskpatterns are interlaced, i.e. when superposed, the strips of the firstpattern are between adjacent strips of the second pattern. An organicmaterial layer, serving as a reflection protective layer, is coated onthe substrate top layer wherein the device pattern is to be configured.The organic material layer is patterned by means of the first mask. Aphotosensitive film is formed on the patterned organic material layerand this film is patterned by means of the second mask, in such a waythat each feature of the photosensitive film pattern is interposedbetween two adjacent features of the organic material layer pattern. Thetotal structure composed of the features of the organic layer patternand the interposed features of the photosensitive film pattern is usedas a mask for etching the substrate top layer. This top layer is theonly process layer used for configuring the relevant level of thesubstrate.

The method described in U.S. Pat. No. 5,716,758, which employs two maskpatterns, is used to print periodic linear patterns and to halve theperiod of the pattern that can be imaged in a satisfactory way. Saidtotal structure of features shows a relatively large topography, i.e.height structure. In the simplest embodiment of FIG. 3 in U.S. Pat. No.5,716,758, the features of the photosensitive film pattern already havea height which is larger than the distance between these features andthose of the organic layer pattern. In the other, more complicatedembodiments wherein more layers are used, the height-to-distance ratiois even larger. Due to the topography of the total structure offeatures, etching of the substrate top, or process, layer through thisstructure with the required accuracy is very difficult, if notimpossible. This renders the method of U.S. Pat. No. 5,716,758 quiteimpractical.

Another problem, not addressed by U.S. Pat. No. 5,716,758, relates tothe physical structure of masks used in optical lithography. Thisproblem becomes more manifest with an increasing feature density in themask pattern. The method of U.S. Pat. No. 5,716,758 uses chrome masks.Such masks consist of a transparent layer of, for example, quartz, whichis covered on one side with a patterned chrome layer. The openings inthis layer determine the pattern that is being projected in a resistlayer. To decrease the minimum feature width that can be imaged with therequired quality, a phase-shift mask, comprising transparentphase-shifting elements, is currently used, which mask may be a chromiumphase-shift mask or a chromium-less phase-shift mask. In a chromiumphase-shift mask, phase-shifting elements are arranged at transitions ofthe chromium layer and the mask substrate. By virtue of theirinterference effects, these elements correct the feature-widthbroadening caused by diffraction at the chromium/substrate transitions.In a chromium-less phase-shifting, mask the pattern features aredetermined completely by phase-shifting elements. Providing a mask withphase-shifting elements means that a layer surface area portion on thismask should be reserved for each pattern feature as compared with a maskwithout phase-shifting elements.

Another recently used technique in the field of optical lithography isthe optical proximity correction (OPC). Small correction elements arearranged at the mask pattern positions, for example at the edges of apattern feature or between two very proximate features, where unwanteddiffraction resulting in feature-width broadening in the resist layerwould occur. These correction elements are not imaged, i.e. they are notresolved, by the projection system, but do diffract the imagingradiation in such a way that they correct said unwanted diffraction.Some space on the mask pattern surface should be reserved for thesecorrection elements.

Still another technique used to enable smaller pattern features to beimaged by the projection system, is adaptation of the illumination ofthe mask and the projection system. Such an adaptation means that theprojection beam does not fill the whole aperture of the projectionsystem, but only a portion or portions of it. This may be a central,circular, portion or an annular part or one portion of each pupil half(dipole) or two portions of each pupil half. However, these types ofillumination cannot be used if a mask pattern comprises a given(forbidden) symmetry, space period (pitch) and/or orientation of thefeatures, because a mask pattern with such forbidden parameters cannotbe imaged without aberrations. There is a different forbidden parameterfor each type of illumination.

It is an object of the present invention to provide means forsubstantially increasing the density of a device pattern that can beconfigured in a substrate while still using a conventional lithographicprojection apparatus. These means relate both to the mask pattern andits manufacture and to the set of processing steps for configuring adevice pattern having sub-critical density, i.e. a density which ishigher than the resolution of the projection system.

According to the invention, the method as defined in the openingparagraph is characterized by the additional steps of:

-   -   forming a stack of at least a first pair of a processing layer        and an anti-reflection layer and a second pair of such layers on        the substrate;    -   coating a resist layer on the top processing layer and        transferring a first sub-pattern in the resist layer;    -   developing the resist layer, thereby forming a first        intermediate pattern corresponding to the first sub-pattern;    -   etching the top processing layer via the first intermediate        pattern, thereby forming a first pattern of device features        corresponding to the first sub-pattern;    -   coating the first pattern of device features with a second        resist layer;    -   transferring a second sub-pattern in the second resist layer;    -   developing the second resist layer, thereby forming a second        intermediate pattern corresponding to the second sub-pattern;    -   etching an underlying processing layer via the etching mask        constituted by the interleaved first pattern of device features        and second intermediate pattern, thereby forming a second        pattern of device feature corresponding to the combination of        the first and second sub-patterns, and    -   removing the second resist layer and the top processing layer.        A processing layer is understood to mean a layer in which device        features are configured when carrying out the method. This term        covers both a temporary layer, for example the above-mentioned        first processing layer, wherein some of the features of the        device pattern are temporarily stored and a final layer, which        is the top layer of the substrate and in which all features of        the device pattern are finally configured.

In the method of the invention, each processing layer is etched via arelatively thin etching mask, constituted by either a patterned resistlayer or, preferably a preceding pair of a patterned processing layerand an anti-reflection layer, so that etching is well controlled andaccurate. As a separate anti-reflection layer is present for eachprocessing layer which will not be attacked during etching of thepreceding processing layer, an intact anti-reflection layer is alwaysavailable. The successively transferred sub-patterns need not beinterlaced, but may comprise overlapping areas and the total maskpattern may have an arbitrary configuration. This configuration may havea very high density, for example the distance between neighbouringdevice features in the substrate layer may be as small as 50 nm. Thisallows the design pattern, in addition to the device features, to beprovided with correction elements like phase-shifting elements and OPCelements without introducing the above-mentioned problems inherent inthese elements. Since device features, which would constitute aforbidden symmetry, a forbidden pitch and/or a forbidden orientation ina design pattern, can be distributed on at least two sub-patterns, theproblem of forbidden parameters can be solved.

An embodiment of the method is further characterized in that at least athird pair of a processing layer and an anti-reflection layer is addedto the substrate side of the stack of layers and in that the followingadditional steps are carried out:

-   -   coating the second pattern of device features with a third        resist layer;    -   transferring a third sub-pattern in the third resist layer,    -   developing the third resist layer, thereby forming a third        intermediate pattern corresponding to the third sub-pattern;    -   etching the third processing layer via the coplanar second        pattern of device features and the third intermediate pattern,        thereby forming a third pattern of device features corresponding        to the combination of the first, the second and the third        sub-patterns; and    -   removing the third resist layer and the second processing layer.        The division of the initial, design, patterns in three        sub-patterns and transferring these sub-patterns in the relevant        substrate layer allows a further increase of the density of the        design pattern with regard to the device features proper but        also with regard to other features like correction elements. By        using a still larger number of sub-patterns and a corresponding        number of processing layers, the density can be increased even        further, provided that the throughput, i.e. the number of        substrates that can be processed per time unit is still        acceptable.

A first embodiment of the method is characterized in that eachsub-pattern is transferred in the corresponding resist layer byoptically imaging a sub-mask, comprising the sub-pattern, in the resistlayer.

This embodiment is most closely linked with the current lithographictechnique. For each sub-pattern, the data representing this pattern aredirectly converted to a physical pattern, the mask pattern, which isimaged as a whole.

A second embodiment of the method is characterized in that at least oneof the sub-patterns is transferred to the corresponding resist layer bywriting this sub-pattern in the resist layer by means of acharged-particle beam.

Writing of individual pattern features by means of a charged-particlebeam, for example an electron beam, may be attractive if the sub-patterncomprises a low number of small particles.

The first embodiment may be further characterized in that all sub-maskpatterns are imaged with radiation of the same wavelength range.

The radiation may be deep UV (DUV) radiation, for example radiation witha wavelength of 248 nm, which is currently used in lithographicprojection apparatus, or a wavelength of 193 nm.

As an alternative, the first embodiment is characterized in that atleast one of the sub-mask patterns is imaged by means of EUV radiationand the other sub-patterns are imaged by means of DUV radiation.

If a lithographic projection apparatus, which employs extreme UV (EUV)radiation, becomes available, it may still be attractive to use such anapparatus only for imaging the most difficult sub-patterns and to imagethe other sub-patterns by means of more conventional apparatus employingDUV radiation. In general, the sub-mask patterns need not be imaged byone apparatus, but several apparatus, either of the same type or ofdifferent types, may be used.

As a further alternative, the first embodiment is characterized in thatat least one of the sub-mask patterns is imaged by means of acharged-particle projection beam.

A similar remark as was made with respect to the EUV projectionapparatus can be made with respect to a projection apparatus employing acharged-particle beam.

The method is preferably characterized in that, in all pairs of layers,the corresponding layers comprise the same material and have the samethickness, with the exception of the processing layer at the side of thesubstrate which has a larger thickness than the other processinglayer(s).

The transfer of the different sub-patterns to the relevant substratelayer can then be performed by using the same settings of theapparatuses for processing the stack layers belonging to thesub-patterns. As the processing layer at the side of the substrate isnot used as an etching mask and the device features are finallyconfigured in this layer, it may be and is thicker than the otherprocessing layer(s).

The method is preferably further characterized in that the material ofeach layer of a pair is resistant against the etching process used foretching the other layer of the pair.

For each pair of layers, this makes it possible to pattern first theanti-reflection layer of the pair by means of a first etching processand then etch the processing layer by means of a different etchingprocess, with the patterned anti-reflection layer being used as a hardmask. When etching the processing layer, the patterned anti-reflectionlayer on top of the processing layer, as well as a blank anti-reflectionlayer of the underlying pair, if present, is not attacked.

The method may be further characterized in that the processing layersused are polysilicon layers.

This embodiment of the method is very suitable for configuring asubstrate layer with transistor gates for which polysilicon layer is avery suitable material. In case a substrate layer has to be configuredwith conductive wiring, at least the processing layer at the side of thesubstrate may be of a metal, like aluminium or copper.

The method is preferably further characterized in that theanti-reflection layers used are dual layers comprising ananti-reflection film and an oxide film on top of it.

The oxide film functions as an isolating layer between theanti-reflection layer under the film and a resist layer above the filmand also forms an etch-stop layer preventing etching of thisanti-reflection layer.

The method is preferably further characterized in that the material of asingle anti-reflection layer or the material of the anti-reflection filmof a dual layer is an inorganic material.

During the process of configuring a sub-pattern in the processing layerbelonging to this sub-pattern, the resist should be removed fromanti-reflection layer portions, because the device features formed inthis processing layer should remain covered with the anti-reflectionlayer. By using an inorganic material for the anti-reflection layer,removal of the resist, which is an organic material, becomesconsiderably easier than in the case where the anti-reflection layer isan organic layer, as in the method described in U.S. Pat. No. 5,716,758.

A preferred embodiment of this method is characterized in that theinorganic material is silicon-oxide-nitride Si_(z)O_(x)N_(y)

A sub-embodiment is characterized in that the inorganic material issilicon-nitride SiN.

This special embodiment of silicon-oxide-nitride, with x=0, z=1 and y≈1,which is a known anti-reflection material in lithography is verysuitable for implementing the present method.

The most practical embodiment of the method is characterized in thatpositive resist layers are used.

Positive resist is by far the most used resist in lithography and willalso be used in the applications of the present method.

However, under certain circumstances a negative resist may be used, forexample, when there is one small feature in a large empty field, or whena pattern of features has to be inverted.

The method used is then characterized in that positive and negativeresist layers are used.

In order to reduce the width of device features in the substrate layer,the method may be characterized in that features of at least one of theintermediate patterns are reduced in size by resist ashing beforeetching such a pattern in the underlying processing layer.

By combining the new method with the known technology of resist ashingboth the distance between device features and the width of thesefeatures can be reduced.

The invention also relates to a solution for the problem ofmanufacturing a mask pattern for configuring a high-density devicepattern in a substrate. Usually, an electron beam write apparatus isused for writing a mask pattern in a resist layer. If such an apparatusis used for writing a mask pattern having a very high density thelimited resolution of such an apparatus and the problem of proximityeffects inherent in such an apparatus become manifest. The proximityeffects are due to the mutual repellence of the electrons in smallconstricted positions of the electron beam and cause smearing of thewritten features.

According to the invention, said problem can be solved by a method ofdistributing pattern features of an initial pattern, which cannot betransferred as such in a satisfactory way, on a number of sub-patterns,which method is characterized by the combination of the followingdistribution rules:

-   -   the number of sub-patterns is as small as possible;    -   in each sub-pattern, device features and their associated        features are arranged in such a way that transfer of each device        feature is independent of the other device features, and    -   in each sub-pattern, the device features are distributed as        uniformly as possible. Satisfying the latter condition means        that optimum transfer conditions can be set for each        sub-pattern, and forbidden symmetries, periods and feature        orientations will not occur. The term associated features covers        all features, which are not transferred to a substrate layer but        are used during transfer to optimize a device feature or to        improve the transfer of this feature. Examples of associated        features are assist features to control the width of a device        feature in a substrate layer, optical proximity correction        elements and scattering bars.

The features of the initial, design, pattern are distributed on a numberof sub-patterns, each of which has a lower density than the initialpattern, and the corresponding sub-masks are easier to manufacture thanone mask comprising all of the features This distribution method is madeapplicable in practice due to the new multiple exposure method asdescribed above, of successively imaging the sub-patterns in one devicepattern on the substrate.

If this method is used for distributing an initial pattern comprising aninitial group of separated polygonal areas, the first rule can besatisfied by the steps of:

-   -   removing, from the initial group, the polygonal areas which        violate the second and/or third rule and putting these polygonal        areas in new groups which satisfy these rules, and    -   putting the remaining initial group and the new groups in        separate sub-patterns.

A preferred embodiment of the distribution method is characterized bythe steps of:

-   -   determining which polygonal areas violate the second and the        third rule;    -   ranking the polygonal areas of the initial group in accordance        with the number of violations occurring for these areas, in        which the polygonal areas with the highest number of violations        have the lowest ranking order number;    -   forming a second group of polygonal areas with the lowest        ranking order number and those with higher ranking order numbers        which, in the second group, still satisfy the first and the        second rule, and    -   repeating the last step for remaining higher ranking order        numbers in the initial group and forming a third and further        groups until all polygonal areas in the remaining initial group        satisfy the second and the third rule.

The invention also relates to a group of lithographic sub-masks obtainedwhen carrying out the distribution method and used for carrying out themanufacturing method as described above. This group of lithographicsub-masks jointly forming a fictitious total mask for configuring asingle device pattern in a layer of a substrate, in which the fictitioustotal mask has a mask pattern comprising separated polygonal areas,which mask pattern cannot be imaged as such in a satisfactory way, ischaracterized in that polygonal areas are arranged in each mask patternof the sub-masks, such that the sub-mask patterns can be imagedsatisfactorily.

A preferred embodiment of the group of lithographic sub-masks ischaracterized in that it comprises sub-masks provided with assistfeatures flanking a device feature and having a specific width forsubstantially determining the width of the image of the relevant devicefeature.

The width of the device features can be controlled by using sub-maskswith assist features.

As regards the type of sub-masks, the group of sub-masks may showdifferent embodiments.

A first embodiment of the group of lithographic sub-masks ischaracterized in that the sub-masks are amplitude masks.

The most commonly used amplitude mask is a chrome mask, i.e. a maskcomprising a mask pattern in the form of a patterned chromium layer on atransparent substrate.

A second embodiment of the group of lithographic sub-masks ischaracterized in that the sub-masks are phase masks.

A phase mask shows a constant transmission throughout the mask patternarea while its mask pattern is constituted by a pattern of phasetransitions.

A third embodiment of the group of lithographic sub-masks ischaracterized in that it comprises amplitude masks and phase masks.

Such a group of sub-masks provides the possibility of forming the devicefeatures with the most appropriate type of mask for each sub-pattern.

In order to refine device features, the group of chromium sub-masks maybe further characterized in that it comprises sub-masks withphase-shifting elements.

For the same reason, the group of phase masks may be characterized inthat it comprises phase masks having amplitude elements at phasetransition positions.

An amplitude element is understood to mean a mask surface area thatchanges the amplitude of radiation incident on it. This area may be anabsorbing area. A combination of phase transitions and amplitudeelements provides the best feature imaging quality.

The group of lithographic sub-masks may be further characterized in thatit comprises sub-masks provided with optical correction elements.

The quality of the imaged mask features can be improved with suchwell-known optical correction elements in the form of, for example,serifs, hammerheads and scattering bars, which are so small that theyare not imaged,.

These and other aspects of the invention are apparent from and will beelucidated by way of non-limitative example with reference to theembodiments described hereinafter.

In the drawings:

FIG. 1 schematically shows an embodiment of a lithographic projectionapparatus by means of which the method can be carried out;

FIGS. 2 a and 2 b show portions of a first mask pattern with a firstfeature and a second mask pattern with a second feature, respectively,for use in the new method;

FIGS. 3 a to 3 h show the consecutive process steps of the method;

FIG. 4 shows an embodiment of the stack of layers used in the method;

FIG. 5 shows a portion of a phase mask;

FIG. 6 shows the theory of image forming of a phase mask;

FIG. 7 shows a portion of a phase mask provided with assist features;

FIG. 8 shows the width of a printed device feature as a function of themutual distance of the assist features;

FIG. 9 shows two device features and their mutual distance obtained bythe new method and the mask of FIG. 7;

FIG. 10 shows a phase mask feature with a stepped phase transition;

FIG. 11 shows a mask feature bend with serif OPC elements;

FIG. 12 shows a square mask feature with serif OPC elements;

FIG. 13 shows a strip-shaped mask feature with a hammerhead OPC element;

FIG. 14 shows a portion of a mask pattern with a scattering bar;

FIG. 15 shows a small portion of a practical mask pattern with serifsand scattering bars;

FIG. 16 shows the sizing of a mask pattern feature;

FIG. 17 shows an original design pattern of a flip-flop circuit;

FIGS. 18 a–18 d show the distribution of the features of this pattern onthree sub-patterns;

FIG. 19 shows the stack of layers used for transferring the mask patternfeature of FIG. 17 in a substrate layer;

FIG. 20 shows a pattern feature with portions at a too short distanceand two sub-mask patterns with overlapping features used for creatingthe pattern feature, and

FIG. 21 shows the technique of resist ashing.

The schematic diagram of FIG. 1 only shows the most important modules ofan embodiment of a lithographic projection apparatus. This apparatuscomprises a projection column accommodating a projection system, forexample, a lens projection system PL. A mask holder MR for carrying amask MA which comprises a mask pattern C to be imaged is arranged abovethis system. The mask holder forms part of a mask table MT. A substratetable WT is arranged in the projection column beneath the projectionlens system. The substrate table is provided with a substrate holder WHfor holding a substrate W, for example a semiconductor substrate, alsocalled a wafer. A radiation-sensitive layer PR, for example aphotoresist layer is coated on the substrate. The mask pattern C shouldbe imaged a number of times in the resist layer, every time in anotherIC area, or die, Wd. The substrate table is movable in the X- andY-directions, such that, after the mask pattern has been imaged in an ICarea, the next IC area can be positioned under the mask pattern and theprojection system.

The apparatus further comprises an illumination system provided with aradiation source LA, for example a mercury lamp or an excimer laser likea Krypton-Fluoride excimer laser, a lens system LS, a reflector RE and acollector lens CO. A projection beam PB supplied by the illuminationsystem illuminates the mask pattern C. The projection system PL imagesthis pattern in an IC area on the substrate W.

The apparatus is further provided with a number of measuring systems.One measuring system is an alignment measuring system for determiningalignment, in the XY-plane, of the substrate with respect to the maskpattern C. Another measuring system is an interferometer system IF formeasuring the X and Y-positions and the orientation of the substrate. Afocus-error detection system (not shown) for determining a deviationbetween the focus, or image field, of the projection system and theradiation-sensitive layer PR on the substrate is also provided. Thesemeasuring systems are parts of servosystems, which comprise electronicsignal-processing and control circuits and actuators by means of whichthe position and orientation of the substrate and the focus can becorrected by means of the signals supplied by the measuring systems.

The alignment detection system uses two alignment marks M₁ and M₂ in themask MA, which marks are shown in the right top section of FIG. 1. Thesemarks are, for example, diffraction gratings, but may also beconstituted by other marks, like squares or strips, which are opticallydifferent from their surroundings. The alignment marks are preferablytwo-dimensional, i.e. they extend in two mutually perpendiculardirections, the X and Y-directions in FIG. 1. The substrate W comprisesat least two alignment marks, two of which, P₁ and P₂ are shown inFIG. 1. These marks are positioned outside the area of the substrate Wwhere the images of the mask pattern have to be formed. The gratingmarks P₁ and P₂ are preferably phase grating and the grating marks M₁and M₂ are amplitude gratings. The alignment detection system may be adouble system wherein two alignment beams b and b′ are used fordetecting alignment of the substrate mark P₂ with respect to the maskmark M₂ and for detecting alignment of the substrate mark P₁ withrespect to the mask mark M₁, respectively. After having traversed thealignment detection system, each alignment beam is incident on aradiation-sensitive detector 3, 3′, respectively. Each detector convertsthe relevant beam into an electrical signal which is indicative of thedegree to which the substrate mark is aligned with respect to the maskmark, and thus the degree to which the substrate is aligned with respectto the mask. A double alignment detection system is described in U.S.Pat. No. 4,778,275, which is referred to for further details about thissystem.

For accurately determining the X and Y-positions of the substrate, thelithographic apparatus comprises a multiple-axis interferometer system,which is schematically indicated by the block IF in FIG. 1. A two-axisinterferometer system is described in U.S. Pat. No. 4,251,160 and athree-axis interferometer system is described in U.S. Pat. No.4,737,823. EP-A 0,498,499 describes a five-axis interferometer system,by means of which both displacements along the X and Y-axes and rotationabout the Z-axis and tilts about the X and Y-axes can be measured veryaccurately.

As indicated in FIG. 1, the output signal Si of the interferometersystem and the signals S₃ and S₃′ of the alignment detection system aresupplied to a signal-processing circuit SPU, for example amicrocomputer, which processes these signals to control signals Sac foran actuator AC. This actuator moves the substrate holder WH in theXY-plane, via the substrate table WT.

The projection apparatus is further provided with a focus-errordetection system, not shown in FIG. 1, for determining a deviationbetween the focal plane of the projection lens system and the plane ofthe radiation-sensitive layer PR. Such a deviation may be corrected, forexample, by moving the projection lens system and the substrate relativeto each other in the Z-direction, or by moving one or more lens elementsof the projection system in the Z-direction. Such a focus-errordetection system, which may be fixed to the projection lens system, isdescribed in U.S. Pat. No. 4,356,392. A detection system by means ofwhich both a focus error and a local tilt of the substrate can bedetected is described in U.S. Pat. No. 5,191,200.

There is a steadily increasing demand for a decrease of the details, thewidth of a device feature, or line, and the distance betweenneighbouring device features, in order to increase the operating speedof the device and/or to increase the number of components in such adevice. The smallness of the details which can be imaged satisfactorilyby a lithographic projection apparatus, of which FIG. 1 shows anexample, is determined by the imaging quality and resolving power of theprojection system. The resolving power, or resolution, is conventionallyimproved by increasing the numerical aperture NA and/or decreasing thewavelength of the projection radiation. A further increase of thenumerical aperture can hardly be expected in practice and a furtherdecrease of the wavelength of the projection beam will pose many newproblems.

A more recent development on the way to imaging smaller pattern detailswith projection systems, which can still be manufactured, is the use ofa step-and-scanning lithographic apparatus instead of a steppinglithographic apparatus. In a stepping apparatus, a full-fieldillumination is used, i.e. the entire mask pattern is illuminated in oneoperation and imaged as a whole on an IC area of the substrate. After afirst IC area has been exposed, a step is made to the next IC area, i.e.the substrate holder is moved in such a way that the next IC area ispositioned under the mask pattern. Thereafter, this IC area is exposed,and so forth until all IC areas of the substrate are provided with animage of the mask pattern. In a step-and-scanning apparatus, only arectangular or circular segment-shaped area of the mask pattern isilluminated and hence also a corresponding sub-area of the substrate ICarea is each time exposed. The mask pattern and the substrate are movedsynchronously through the projection beam, while taking themagnification of the projection system into account. In a continuousprocess, subsequent sub-areas of the mask pattern are then each timeimaged on corresponding sub-areas of the relevant IC area. After imagingthe entire mask pattern on an IC substrate in this way, the substrateholder performs a stepping movement, i.e. the beginning of the next ICarea is moved in the projection beam. The mask is then set, for example,in its initial position, whereafter said next IC area is scan-exposed.As only the central part of the image field is used in thestep-and-scanning method and only this part thus needs to be correctedfor optical aberrations, a relatively large numerical aperture can beemployed. In this way, the width of the device features and theirinterspaces, which can be imaged with the required quality, can bedecreased to a certain degree. However, this way of increasing thedensity of device patterns will not be sufficient for coming generationsof ICs and other devices. Moreover, due to imperfections of theapparatus, like optical aberrations, and of the lithographic processes,the theoretical limit, set by the numerical aperture, the wavelength andthe scanning principle will not be reached in practice.

The problem of considerably increasing the density of a device patterncan be solved by a new method of distributing the features of theinitial device pattern on a practical, i.e. limited, number ofsub-patterns and by a new method of superposed transfer of thecorresponding sub-masks in the substrate. The transfer method will beexplained with reference to two neighbouring device features, or strips.Each of these strip-shaped features form part of a separate maskpattern.

FIG. 2 a is a top view of a very small portion of the first mask patternC1 with only a first feature 10. In the simplest case, the mask is achrome mask and the feature 10 is a stroke-shaped opening in a chromelayer 12. FIG. 2 b shows the first mask pattern C2 with the secondfeature 14, i.e. a stroke-shaped opening in a chrome layer 16.

FIG. 3 a shows a cross-section of the stack of layers, which is used totransfer the mask features to the substrate. In this Figure, referencenumerals 20 denotes the top of a substrate, for example a semiconductorsubstrate. Layer 22 is a first processing layer, for example apolysilicon layer, which is coated with a first anti-reflection layer24. Layer 26 is a second processing layer, preferably of the samematerial as the first processing layer. The second processing layer iscoated with a second anti-reflection layer 28, preferably of the samematerial as the first anti-reflection layer.

The mask features 10 and 14 are transferred to the first processinglayer 22 in the following way. The stack of layers is provided with aresist layer 30 and the first mask pattern is imaged in this layer. Theresist layer is illuminated with a stroke of radiation at a positioncorresponding to the position of the feature 10 in mask pattern C1.After development of the resist and resist stripping, i.e. removal ofthose parts of the resist layer which have not been illuminated in thecase of a positive resist, a stroke 32 of resist material remains on thelayer 28, as shown in FIG. 3 b. The anti-reflection layer 28 is thenetched first and then the second processing layer 26 is etched, usingthe resist pattern as an etching mask. Feature 10, and other features(not shown) of the first mask pattern have then been transferred tofeature 35, i.e. a ridge of processing layer 26 material, as shown inFIG. 3 c. On top of this ridge, there is still a stroke 34 ofanti-reflective material. In the next step, the stroke 32 of resistmaterial is stripped. As the resist is an organic material and theanti-reflection layer is made of an inorganic material, the resist caneasily be removed without attacking the anti-reflection layer. As shownin FIG. 3 d, after removal of the resist, the top of the remaining stackof layers is constituted by an anti-reflection layer, both at theposition of the feature 35 and other positions of the top surface.Instead of etching the processing layer via the patterned resist layer32, it is also possible, and even preferred, to etch only theanti-reflection layer via the patterned resist layer and then strip theresist layer. The processing layer is then etched via the patternedanti-reflection layer 34, which forms a so-called hard mask for theprocessing layer.

After the first feature 35 has been transferred in this way, the stackof layers is coated with a new resist layer 36, as shown in FIG. 3 e.The second mask pattern comprising mask feature 14 is imaged in thisresist layer. After development of the resist layer 36 and removal ofthe exposed parts of this layer, a stroke 38 of resist material remainson the anti-reflection layer 24, as shown in FIG. 3 f. Theanti-reflection layer 24 and the first processing layer 22 are thenetched, using the composed structure of feature 35 (with anti-reflectionlayer 34 on top) and the resist stroke 38 as an etching mask. Theanti-reflection layer 34 and the second processing layer 35 are removedsimultaneously with the etching of anti-reflection layer 24 and firstprocessing layer 22. The patterned resist layer 38 is then stripped. Themask features 10 and 14 are now transferred to device features 40 and44, respectively. These device features are ridges of processing layer22 material. Both device features are covered by a stroke ofanti-reflective material 42 and 46, respectively, shown in FIG. 3 g. Ifno further features have to be transferred, the strokes 42 and 44 ofanti-reflective material are removed so that two device features 40, 44forming the required structure in the top layer of the substrate remain.

As the mask features corresponding to the device features 40 and 44 needno longer be imaged simultaneously, it is no longer the resolution ofthe projection system that determines the minimum distance d between thefeatures 40 and 44. This minimum distance is now determined by theaccuracy with which mask feature 14 can be positioned with respect todevice feature 35 previously configured in the second processing layer26. Lithographic projection apparatuses are available now, which havevery advanced alignment servosystems. With such a system, a singlemachine overlay accuracy better than 10 nm may be obtained, i.e. theerror in position of a feature in a resist layer with respect to anunderlying previously configured device feature is smaller than 10 nm.By using the new method with such an accurate alignment servosystem, aminimum distance d of the order of 50 nm between the device features canbe obtained. The new method makes optimum use of the accuracy ofalignment servosystems that are already available.

This method has the advantages that an intact anti-reflection layer ispresent under the resist layer during each illumination of a resistlayer and that the height of the etching mask used for etching theprocessing layers remains small. For example, the height of an etchingmask may be as small as the sum of the thickness of an anti-reflectionlayer and a processing layer. Due to the small height of the etchingmasks, optical proximity effects can be neglected.

The use of two mask patterns and an alignment servosystem, as in theembodiment of FIGS. 3 a–3 h, for realizing two neighbouring devicefeatures provides the largest degree of freedom with respect to maskpattern design. If the device pattern is a period pattern with a smallperiod, it is possible to use one mask pattern and to move this pattern,after the first device feature has been configured, over a distancewhich is equal to the required distance between the two device features.

Each anti-reflection layer 24, 28 may be a double layer of ananti-reflection film and a thin oxide layer on top of it. The oxidelayer forms an isolation between the anti-reflection film and a resistlayer coated on this double layer when the underlying processing layeris to be patterned. Moreover, the oxide layer forms an etch stoppinglayer, preventing unwanted etching of the anti-reflection film.

The anti-reflection film is made of an inorganic material, for examplesilicon-oxyde-nitride Si_(z)O_(x)N_(y). A specific embodiment of thismaterial, namely silicon nitride (z=1, x=0 and y≈1) preferably is usedfor the anti-reflection film. This material is already used in thelithographic field and is also very suitable for implementing thepresent method.

FIG. 4. shows a stack of layers comprising dual anti-reflection layers.Reference numeral 20 denotes the silicon substrate, or wafer. A verythin, so-called gate oxide, layer 21, which isolates the substrate fromthe processing layer 22, may be arranged, between this substrate and thefirst processing layer 22, for example of polysilicon. An SiNanti-reflection film 24′ and a top oxide layer 25 are arranged on top ofthe first processing layer. The second processing layer 26 is arrangedon top of layer 25. An SiN anti-reflection film 28′ and a top oxidelayer 29 are arranged on top of the processing layer 26. A resist layer30 is coated on this double layer.

In a practical embodiment of the stack of layers, the gate oxide layer21 has a thickness of 2 nm. The polysilicon processing layers 22 and 26have a thickness of 100 nm and 20 nm, respectively. Each anti-reflectionfilm 24′, 28′ has a thickness of 23 nm and their top layers 25 and 29have a thickness of 12 nm each. In this embodiment, the etching mask hasa maximum height of 55 nm. After the first mask pattern feature 10 hasbeen imaged in the resist layer 30 and this layer has been developed,the top oxide layer 29 is dry-etched for 20 mseconds. The resist is thenstripped, using a standard resist strip and the stack is wet-cleaned.The second polysilicon processing layer 26 is etched via the hard maskformed by the patterned top oxide layer 29 and anti-reflection film 28′in a 5-second cleaning step, a 10-second main etching step and a10-second over-etching step. During this etching, no resist is presenton the stack. After the second mask pattern feature 14 has been imagedin the second resist layer 36 and this layer has been developed, the topoxide layer 25 is etched in the same way as layer 29. The firstpolysilicon processing layer 22, which is five times thicker than thesecond processing layer 26, is etched via the patterned oxide layer 25and anti-reflection film 24′ in a 30-second main etching step and a30-second over-etching step.

The density of a device feature pattern is not only determined by thedistance between neighbouring device features, but also by the width ofthe device features. The contrast of the image formed in a resist layerof two neighbouring mask pattern features decreases and the width ofthese features formed in a processing layer increases when the distancebetween the features decreases. Said contrast can be enhanced by using achrome mask provided with phase-shifting elements, instead of aconventional pure chrome mask, which is a transmission mask. Thetechnique of improving contrast of the images formed in the opticallithography was first proposed by Levenson et al in the article:“Improving resolution in Photolithography with a Phase-Shifting Mask” inIEEE Transactions on Electron Devices, Vol.ED-29, no.12, December 1982,pp 25–32. The conventional transmission mask comprises a transparent,for example, quartz substrate covered by an opaque, preferably chromelayer with apertures. These apertures define the desired intensitypattern and thus the device pattern to be printed in a layer of thesubstrate. When illuminating such a transmission mask withelectromagnetic radiation, the electric field of this radiation has thesame phase at every aperture. However, due to diffraction of theradiation at the edges of the apertures and the limited resolution ofthe projection lens system, the electric field patterns at the substratelevel are spread. A single small mask aperture thus provides a widerintensity distribution at substrate level. Constructive interferencebetween waves diffracted by adjacent apertures enhances the electricfield between the projections of the apertures at substrate level. Asthe intensity pattern is proportional to the square of the electricfield, this pattern of two adjacent mask apertures is spread evenly to afairly high degree and does not show two pronounced peaks at thepositions of the projected apertures.

FIG. 5 shows a small portion of a chromium mask provided withphase-shifting elements. This mask comprises a transparent substrate 40covered by a chromium layer 42. Apertures 44 and 46 in this layerconstitute two features of the mask pattern. One of the two apertures iscovered with a transparent phase-shifting element 48. This element has athickness d of λ/2(n−1), wherein n is the index of refraction of theelement material, and λ is the wavelength of the projection radiation,such that the waves transmitted through the adjacent apertures 44 and 46are 180° out of phase with each other. Destructive interference nowoccurs between the waves diffracted by the adjacent apertures so thatthe electric field and thus the intensity between the projections of theapertures at wafer level is minimized. Any projection system willproject the images of such a phase-shifting mask with a betterresolution and higher contrast than a corresponding mask without phaseshifters.

A “chrome-less” phase-shifting mask, as disclosed in EP-A 0.680.624 canprovide a similar improvement with respect to contrast and featurewidth. The pattern structure, defining the device structure, of such amask does not comprise a pattern structure of chromium, or other opaquematerial, but the pattern is a pattern of phase transitions. FIG. 6shows a small portion of a phase mask with one phase transition, or maskfeature, 52. The reference numeral 50 denotes the transparent masksubstrate. The phase transition is the transition between the surface 54of the substrate and a recess 55. The depth of this area is denoted bye. As the mask is transparent to the projection PB, the transition is aphase transition to this beam. This means that the portion of theprojection beam PB, which has passed the recess area 55, has a differentphase than a beam portion which has passed through a surface area 24.The phase difference φ (in radians) between the beam portions is givenby:φ=(n ₂ −n ₁).e.2π/λwherein n₂ is the refractive index of the mask substrate, n₁ is therefractive index of the surrounding medium, which is usually air withn₁=1, and λ is the wavelength of the projection beam, which is a beam ofelectromagnetic radiation.

After having passed through the phase structure, the size of theelectric field vector E of the beam as a function of the position xshows the variation of graph 57. The position of the vertical slope 58in this graph corresponds to the position of the phase transition 52.After passage through the projection system PL, representedschematically by a single half lens element in FIG. 6, the size of theelectric field vector E′ as a function of the position x shows thevariation of graph 60. The vertical slope 58 of graph 57 has beenconverted to an oblique slope 61 in graph 60. This is a result of thefact that the projection lens system PL is not an ideal system, but hasa point-spread function. A point is not imaged as a point, but itsradiation is more or less spread across an Airy-pattern. If theprojection system were ideal, the electric field vector E′ would bevertical, as indicated by the broken line 62. The size of the electricfield vector E′ represents the amplitude of the projection beam so thatgraph 60 shows the amplitude of the beam as a function of the positionin the plane of the resist layer 30 (36). Since the intensity of thebeam is equal to the square of the amplitude (I=E′²), this intensityshows, as a function of the position x, the variation of graph 64. Theedge 61 of graph 60 has changed over to two edges with opposite slopes65 and 66, which means that a line-shaped phase transition of thephase-shifting mask pattern is imaged in a stroke having a certain widthwi.

Instead of a transmission pattern, also a reflective phase-shifting maskpattern, i.e. a pattern wherein both the recess area 55 and thesurrounding areas 54 are reflective, may be used. In the latter case theoptimum depth, or height, of the recess area is equal to a quarter ofthe wavelength.

A phase-shifting mask may also be provided with amplitude, for examplechrome, elements at the positions of the phase transitions. Such anamplitude element 56, shown in FIG. 6 by broken lines, blocks theradiation incident on it. With a combination of a phase transition andamplitude element, the latter determines the position of the devicefeature and the former determines the width of this feature.

In a concrete application, the width of the strip imaged in the resistlayer is dependent on, inter alia, the numerical aperture of theprojection system and the coherence value of the illumination. Thecoherence, or σ−, value is the ratio of the cross-section of theprojection beam in the plane of the pupil of the projection system andthe aperture of this system. The a value thus indicates the degree towhich the projection system is filled by the projection beam and isusually smaller than one. The width of a device feature, for example atransistor gate, formed in the relevant layer of the substrate afterdeveloping the resist and etching is also dependent on the exposure doseused in the lithographic projection apparatus. The exposure dose is theamount of projection, or exposure, radiation, which is incident on aresist layer area during imaging of a mask feature on this area. Oncethe values of the parameters of numerical aperture, coherence value andexposure dose have been set, all phase transitions of the phase maskpattern are transferred to strips in the substrate layer, of which allhave the same width. For example, at an exposure wavelength of 248 nm, anumerical aperture NA=0.63 and a coherence value σ=0.35, and a featurewidth of the order of 100 nm can be obtained. However, in practice,device features with different widths, for example, transistor gateswith different gate lengths are required in one IC device. Moreover, afurther reduction of the feature width is required.

In a technique of adding two assist features to a phase transition, theminimum width of device features can be decreased considerably and thiswidth can be varied over a considerable range, without changing theabove-mentioned parameters.

FIG. 7 shows the phase transition of FIG. 6 provided with such assistfeatures 70 and 71 at both sides of the transition. These features havesuch small (sub-resolution) widths that they are not imaged as such inthe photoresist, but have a diffracting effect and may therefore becalled scattering bars. They may consist of chromium and have a widthof, for example, 300 nm. The bars 70 and 71 are arranged symmetricallywith respect to the phase transition 52 and their mutual distance is,for example, 2.5 μm. The bar 70 rests on the upper surface 54 of themask substrate. To provide a support for the bar 71, a small column 73of mask substrate material should be saved when making the phasetransition. The dimensions of this column can be optimized for example,wet etching.

Although the scattering bars 70 and 71 belonging to the phase transition52 are not transferred to the resist layer, they have an effect on theimage of the transition. A portion of the exposure radiation incident ona scattering bar is directed towards the intensity peak 58 of FIG. 6 andinterferes with the radiation of the original intensity peak and thusmodifies this peak. The technique of adding assist features is based onthe recognition that the width of the image of a feature formed in theresist layer, and thus the width of the device feature printed in thesubstrate layer that is momentarily configured, is mainly determined bythe mutual distance between a pair of scattering bars. In addition, alsothe width of the scattering bars, the transmission of these bars and thephase shift introduced by these bars have their influence on the widthof the image of the device feature formed in the resist.

FIG. 8 shows the variation of the width of a printed device feature,also called line width, W_(IF) as a function of the mutual distance p ofthe scattering bars. For this example, the width w_(b) of the bars is 90nm on the substrate level, and 360 nm on the mask level if theprojection system has a magnification M=¼. The broken-line graph Vsgives the line widths obtained in a computer simulation and thesolid-line graph Ve gives the line widths obtained from experiments.These experiments were performed with a stepping lithographic apparatuswith a coherence value σ=0.35 and a numerical aperture NA=0.63. Theexperimental depth of focus was approximately 0.5 μm, also for thefeatures with the smallest width. The latitude for the exposure dose wasapproximately 10%.

The graph Ve in FIG. 8 shows that the printed device feature widthw_(IF) decreases if the mutual distance p increases. It shows also thatthe printed feature width can be set accurately to any value between 270nm and 50 nm, by simply varying the distance p between the scatteringbars between 250 nm and 600 nm (at substrate level). The pair of barsthus allows a choice of a printed device feature width from a broadrange, the largest width of this range being more than five times largerthan the smallest width.

By way of example, FIG. 9 shows a cross-section of two device features80 and 81 etched in the first processing layer of polysilicon, in whichthe new double exposure and a phase mask with scattering bars have beenused. The Figure demonstrates that device features having a width ofapproximately 60 nm and a mutual distance p of approximately 60 nm canbe manufactured. For printing these device features, the stack of layersof FIG. 4 and the processing steps cited with respect to this stack wereused. The projection apparatus used operates at a wavelength of 248 nmand has a numerical aperture NA=0.63 and a coherence value σ=0.35.

As already mentioned, the width of the printed device features is mainlydetermined by the distance p between the scattering bars. However, alsothe width w_(b) of these bars, their transmission and the phase shiftintroduced by these bars in the projection beam have their influence onthe final width. The parameters W_(b), transmission and phase can beused for fine tuning of the width of the printed device features.

In principle, an assist feature may also be constituted by a phasetransition instead of by an opaque bar or strip. The width of such aphase transition assist feature should be very small in order to preventthat such a feature would be imaged as such in the resist layer. Thismakes it more difficult to manufacture a mask pattern with assistfeatures in the form of phase transitions.

Assist features, which, in the case of a transmission mask, have a lowertransmission than their surroundings, form a better alternative toopaque, assist features. The lower transmission assist features may becalled attenuated assist features and are comparable with the devicefeatures of the so-called attenuated phase mask. As described in PCTpatent application WO 99/47981, an attenuated phase mask is a specificembodiment of a phase mask wherein the mask pattern features areconstituted by strips having a transmission which is, for example, ofthe order of 5% smaller than the transmission of their surroundings.Such mask pattern features have both a phase effect and an amplitudeeffect on the projection beam.

The method of the invention and the specific structure of the stack oflayers according to FIGS. 3 and 4 allows the use a of third, a fourthetc, sub-mask and imaging these masks in a third, a fourth, etc. resistlayer. A third, fourth, etc. processing layer as well as a third,fourth, etc. anti-reflection layer (FIG. 3), or an anti-reflection layerplus a top oxide layer, should then be added to the stack of layers ofFIG. 3 or 4. As all etching masks for etching the processing layers havea small topography, with a maximum height which is equal to the sum ofthe thickness of a processing layer and an anti-reflection layer,etching can be performed in a very accurate way. The required number ofsub-masks used and thus the number of successive exposures of the stackof layers depends on the complexity and density of the total maskpattern. The complexity and density of a total mask pattern is not onlydetermined by those of the device pattern to be configured in asubstrate layer, but also by other features which may be added to themask pattern for different purposes.

The simplest mask structure for a mask pattern is a transmission, forexample a chromium, mask. Each pattern feature of a transmission mask,also called binary mask, will be imaged and corresponds to a feature ofthe device feature to be configured in the relevant substrate layer. Analternative for a transmission sub-mask is a reflective sub-maskcomprising a pattern of reflective and non-reflective areas. Areflective mask also belongs to the binary mask category.

A more complex mask structure for a mask pattern is a transmission, orreflective, mask provided with phase-shifting elements. Adding phaseshifting elements means that the density of the mask pattern isincreased.

Another mask structure for a mask pattern is a phase mask, which may bea transmission mask or a reflective mask. A transmission phase mask hasbeen discussed herein before with reference to FIG. 6. This Figure showsonly one vertical transition, from the mask surface 54 to the recessedarea 55, which transition is used to realize a strip-shaped illumination68 of the resist layer. However, the mask area used for creating thisstrip, and thus a corresponding device feature in the substrate layercomprises a second transition, from the recessed area 55 to the masksurface 54, as shown in FIG. 10. In this Figure, the first transition isindicated by the solid vertical line 53 and the second transition isindicated by the broken vertical line 56. In order to prevent the secondtransition from being also imaged in the resist layer, the transition 56causing a phase shift of 180° may be sub-divided into a number ofsub-transitions each causing a smaller phase shift. For example, threesub-transitions 59 ₁, 59 ₂ and 59 ₃ each causing a phase shift of 60°may be present at the trailing edge of the recess area 55. Projectionbeam portions from the sub-transitions have different phases andradiation from the area of the sub-transitions will be smeared out andnot concentrated in a small area, like area 68 in FIG. 6. Additionalspace in the mask pattern is needed for the sub-transitions. Some spaceis also required for the assist features, or bars, 70 and 71 in thephase mask of FIG. 7, which assist features are used to control thewidth of device features.

As the projection system of an optical lithographic projection apparatusis employed at its resolution border, imaging of mask pattern featuresis no longer perfect and is accompanied by aberrations, especially atthe edges of these features. For example, and as shown in FIG. 11, a 90°bend 90 of a feature may be imaged as a curved bend 92 and a squarefeature area 96 may be imaged as a circular area 98, as shown in FIG.12. To correct for these aberrations, small, so-called optical proximitycorrection (OPC) elements 93 and 99, respectively, may be added to theoriginal mask pattern. The OPC elements 93 and 99 are called serifs. Asshown in FIG. 13, a straight edge 101 of a strip-shaped mask patternfeature may be imaged as a curved edge 103. An OPC element 105, called ahammerhead, may be added to the original mask pattern in order to obtainan image with a straight edge. As shown in FIG. 14, some patternfeatures may be arranged close to each other, while the next feature 109is located at a larger distance. When imaging such a pattern portion, itmay happen that an artefact is formed in the resist layer between theimage of the last of feature 107 and the feature 109. To preventformation of such an artefact, a small scattering bar 110 may be addedto the original mask pattern. The scattering bar is not imaged, butdiffracts projection radiation and, due to interference with theradiation, which would form the artefact, causes the artefact not to beformed. As shown by way of example in FIG. 15, a mask pattern maycomprise both OPC elements and scattering bars. This Figure shows asmall portion of a mask pattern that is used in practice. The portionshown comprises a large number of serifs 99 and two mutuallyperpendicular scattering bars 109.

Due to imperfections of the imaging step and/or other several processsteps, it may happen that the transfer of a mask pattern feature in aprocessing layer is accompanied by a certain shrinkage, i.e. the widthor length of the printed device feature is smaller or shorter thancorresponds to the mask feature. To correct for such shrinkage, thewidth or length of the original design feature may be increased, whichis known as sizing of mask features. This is illustrated in FIG. 16,wherein the original design feature 112 is indicated by broken lines andthe sized feature 114 is indicated by solid lines.

Although the additional space in the mask pattern required for OPCelements and sizing is relatively small per se, application of the OPCand sizing technique may bring a corrected pattern feature too close toone or more neighbouring features. This would mean that the OPC andsizing techniques would not be applicable.

The above-mentioned phase-shifting elements, assist features, OPCelements, scattering bars can be generally referred to as featuresassociated with a device feature or associated features.

The problem of a too high density, or too small distance between maskpattern features, which may occur both in a binary mask, a phase mask, aphase mask with assist features, or in each of these masks provided withOPC elements, scattering bars or sized features can be solved bydistributing device features with their associated features on a numberof sub-patterns and by superposed transfer of the sub-patterns to therelevant substrate layer by means of the special stack of layerdiscussed hereinbefore.

The distribution method in combination with the special lithographicstack of layers can also be used for solving the problem that maskpattern portions showing certain symmetries, called forbiddensymmetries, cannot be imaged with the required quality due to projectionsystem aberrations which become manifest for such symmetries. Forexample, if a mask pattern portion shows symmetry along three axes, theimage of this portion may be disturbed due to the three-point aberrationof the projection system. This kind of aberration is discussed in thearticle: “Zernike Coefficients: Are they really enough?” by C. Progleret al in: Proceedings of the SPIE Vol. 4000, 2000, pp.40–46.

Moreover, if a specific kind of illumination of the mask pattern isemployed in the projection apparatus, for example a so-called off-axisillumination like a dipole or quadrupole illumination, mask patternportions showing specific periodicities, called forbidden symmetries,cannot be imaged with the required quality. For example, if an off-axisbeam, for example a beam with an annular cross-section illuminates themask pattern, for imaging the mask pattern, only sub-beams diffracted infirst diffraction orders are used. This means that only first ordersub-beams should fall completely within the pupil of the projectionsystem, while second and further higher order sub-beams should not fallwithin this pupil. As the angles at which first a higher order sub-beamsare diffracted by a mask pattern portion are determined by the periodwithin this portion, i.e. the smaller the period, the larger thediffraction angle, the requirement can be met only for a given range ofperiods. For pattern periods smaller than those of said given range, thefirst-order beams will shift out of the pupil and the image formed willbe incomplete. For pattern periods larger than those of said givenrange, second and other higher-order beams will shift into the pupil andcause a disturbance of the image formed. Thus, periods outside saidgiven range are forbidden. In the case of quadrupole illumination, i.e.only portions of the four quadrants of the pupil are illuminated, whileother periods and symmetries in the mask pattern are forbidden. Thedisturbing effect of forbidden periods and symmetries which occur in theoriginal design mask pattern can be substantially reduced, or eveneliminated, by distributing the features of this pattern on a number ofsub-mask patterns. As these sub-patterns are separately imaged, theillumination conditions for these sub-patterns can be adapted to theirpattern structure so that they can be imaged in an optimum way.

In practice, the optimum illumination conditions for pattern featuresextending in the x-direction of the two-dimensional, X-Y, pattern may bedifferent from those conditions for pattern features extending in theY-direction. According to the present invention, the X features and theY-features can be arranged in a first sub-mask pattern and in a secondsub-mask pattern, respectively, and both patterns can be imagedsuperposed, using the specific stack of layers. Optimum illuminationconditions can be chosen, both for the X-features and for theY-features.

The invention also provides an efficient method of distributing theoriginal mask pattern features on sub-mask patterns. Efficient isunderstood to mean that none of the sub-mask patterns comprises anyaberration-sensitive pattern portion, while the number of sub-masks isas small as possible. The term aberration-sensitive pattern portion isunderstood to mean a pattern portion, which, when imaged under theprescribed illumination conditions, would result in an image sufferingfrom aberrations. The aberration-sensitivity may be caused by:

-   -   a minimum distance between pattern features, assist features,        OPC elements and scattering bars mutually and with respect to        each other, which is too small in view of the resolution of the        projection system;    -   a symmetry in the feature pattern for which the projection        system has an inherent incapability to image without aberration;    -   a spatial period in the feature pattern which is incompatible or        less compatible with the kind of illumination prescribed, and    -   an orientation, in the mask plane, of features which is less        compatible with the kind of illumination prescribed.

An embodiment of the distributing method will be described withreference to a flip-flop circuit. The starting point is a layout, ordesign, of the circuit in the form of a standardized file, for example aGDS₂-file. This file consists of a long list of mask features, alsocalled polygons, which together constitute the circuit. FIG. 17 shows aportion of the original design mask pattern of the flip-flop circuit.The pattern comprises twelve polygons 121 to 132. A general rule forthis pattern is that the distance between neighbouring parts of thepolygons should be larger than a given minimum distance, which isdetermined by, inter alia, the resolution of the projection system. Thepositions in the mask pattern, where this rule is violated, are denotedby the hatched small strokes 135. In total, there are 18 of suchpositions. As a first step, the polygon with the largest number ofviolation is selected and this polygon, polygon 123 showing sixviolations, is moved to a first sub-mask pattern 120 a, shown in FIG. 18a. In the next step, the polygon with the largest number of violationsis selected from the remaining polygons. This is polygon 126 showingfour violations. As polygon 126 is positioned at a sufficient distancefrom polygon 123, it can also be moved to the first sub-mask pattern 120a without introducing violations in this sub-mask pattern. The rest ofthe original mask pattern comprises three polygons, 121, 127 and 130each showing three violations. These polygons cannot be moved to thefirst sub-mask pattern because their distance to the polygons 123 and126 is too small. The polygons 121, 127 and 130 should therefore bemoved to another sub-mask and, as no violations occur between them, theycan be moved to a single sub-mask. The sub-mask pattern 120 b comprisingthe polygons 121, 127 and 130 is shown in FIG. 18 b. The rest of theoriginal mask pattern, comprising polygons 122, 124, 125, 128, 129, 131and 132, does not show any violation so that these polygons can remainin a single sub-mask pattern, which is the third sub-mask pattern shownin FIG. 18 c. FIG. 18 d has been added to show in one view the threesub-mask patterns, which are distinguished from each other by differentgrading.

To image the three sub-mask pattern in a superposed manner, a stack oflayers comprising three processing layers, as shown in FIG. 19, has tobe used. The stack of FIG. 19 is similar to that of FIG. 4, but extendedwith a third processing layer 26′, a third anti-reflection layer 28″ anda third oxide layer 29′. These layers preferably have the same thicknessand comprise the same materials as layers 26, 28′ and 29.

The same method described hereinbefore, for of transfer a mask pattern,to a substrate layer wherein polygons or device features are too closeto each other, can also be used for transferring a mask pattern whereinthe device features are at a sufficient distance, but to which OPCelements, scattering bars or assist features have to be added for anaccurate and reliable imaging of the device features. The method canalso be used for transferring a mask pattern wherein device features aretoo close to each other and which comprises also OPC elements,scattering bars and assist features. The distribution on the sub-maskpattern should be such that said OPC elements, scattering bars andassist features are moved to the sub-mask pattern of the device featureto which they belong. As already remarked, the method can also be usedfor removing forbidden symmetries and periods from the mask pattern andfor preventing pattern features extending in a first, X-, direction anda second, Y-, direction from being imaged under the same illuminationconditions. If only the X-pattern features and the Y- pattern feature ofa pattern should be moved to a first and a second sub-mask pattern,respectively, a stack of layers with only two processing layers isneeded.

If a number of different illumination conditions are needed for imagingdifferent sub-mask patterns, a corresponding number of projectionapparatus can be used, each adapted to the specific sub-mask pattern tobe imaged by it. In general, different projection apparatus can be used,irrespective of the kind of illumination, for imaging the sub-maskpatterns needed for configuring a substrate layer.

Up to now it has been assumed that each sub-pattern of features istransferred to the relevant substrate layer by optically imaging asub-mask comprising this pattern in the resist layer. However, it isalso possible to transfer at least one sub-pattern to the resist layerby means of a projection apparatus other than an optical projectionapparatus, for example a charged-particle beam apparatus like an E-beamprojection apparatus. Instead of using a mask and imaging this mask, asub-pattern can also be transferred to a resist layer by writing thispattern in the layer. The writing apparatus may be a charged-particlebeam apparatus, like an electron beam-writing apparatus. The data forthe at least one sub-pattern is supplied to the E-beam apparatus whichthen writes the sub-pattern directly in a resist layer on the stack oflayers. The resist layer may be of the same material as that of thelayer wherein a mask pattern is imaged optically. The use of an E-beamapparatus is attractive when an original mask pattern comprises arelatively small number of small features and/or the number of devicesto be manufactured is small.

In the example of FIGS. 18 to 18 d, the features of one of the sub-maskpatterns 120 a to 120 c do not have any overlapping portion withfeatures of one of the other sub-mask patterns. However, stripsbelonging to one feature, for example the two left strips 136 and 138 offeature 121 (FIG. 18 b) may be too close to each other. A distributionon sub-feature level can then be carried out, i.e. portions belonging toone feature are distributed on different sub-mask patterns, as shown byway of example in FIG. 20. A design feature 140 comprises a horizontalstrip 142 and three vertical strips 144,146 and 148, where 146 and 148are too close to each other. A first sub-mask pattern is formed whichcomprises a feature 140′ having strips 142′, 144′ and 146′ correspondingto the strips 142, 144 and 146, respectively. A strip 148′ with a lengthcorresponding to that of strip 148 in the design pattern should bearranged in a second sub-mask pattern. An essential condition is, thatthere is no opening between the strips 148 and 142 in the printedfeature in the substrate layer, i.e. strip 148 should merge with strip142. In order to avoid that stroke 148 does not merge with strip 142 inthe printed feature, the strip 148′ is lengthened so that this strip148″ in the second sub-mask pattern shows some overlap with strip 142′in the first sub-mask pattern. Such an overlap does not cause anyproblem in the method of the invention.

Instead of using only positive resist layers, as in the embodiments ofFIGS. 3 a to 3 h, also a combination of positive resist layers and anegative resist layer may be used. In general, a negative resist layerwill be used in combination with a dark field mask if a small feature ina blank (empty) area has to be imaged and when a mirror inversion of apattern is required.

The distance between the features printed in the relevant substratelayer can be considerably reduced by the combination of the featuredistribution method and the stack of layers. In cases where a reductionof the width of features is required, the known technique of resistashing can be added as a further processing step. FIG. 21 shows theprinciple of his technique with reference to an embodiment wherein aphase-shifting mask 180 is used, which has chromium strips 184 at thetransitions 182. After exposure of a resist layer with such a mask, theintensity of the radiation received by the resist at the location of thetransition is indicated by the curve 186. The horizontal line 188through the curve 186 denotes the threshold for development. Afterdevelopment, a resist pattern on substrate 190 is obtained. A resistfeature 192 has a given width Wr and height Hr. The resist pattern isthen etched with an O2 plasma etch. At both flanks and at the top of theresist feature, resist material is converted to an ash-like substanceand removed. The result of this resist ashing is a considerably reducedresist feature 194. In this way, the width of the resist feature can bereduced by several tens of percent. Resist ashing is described in thearticle: “Extension of Kr—F lithography to sub-50 nm pattern formation”by S. Nakao et al. in SPIE, Vol. 4000, 2000, p.358.

1. A method of manufacturing a device in at least one layer of asubstrate, the method comprising the steps of: providing a designpattern comprising pattern features corresponding to device features tobe configured in said layer; transferring the design pattern in a resistlayer provided on said substrate layer; removing material from or addingmaterial to areas of said layer, which areas are delineated by thepatterned resist layer; a number of sub-patterns each comprisingdifferent portions of the design pattern being successively transferredin a corresponding number of resist layers, which are consecutivelycoated on said substrate layer, characterized by the steps of: forming astack of at least a first pair of a processing layer and ananti-reflection layer and a second pair of such layers on the substrate;coating a resist layer on the top processing layer and transferring afirst sub-pattern in the resist layer; developing the resist layer,thereby forming a first intermediate pattern corresponding to the firstsub-pattern; etching the top processing layer via the first intermediatepattern, thereby forming a first pattern of device featurescorresponding to the first sub-pattern; coating the first pattern ofdevice features wit a second resist layer; transferring a second sub-pattern in the second resist layer; developing the second resist layer,thereby forming a second intermediate pattern corresponding to thesecond sub-pattern; etching an underlying processing layer via theetching mask constituted by the interleaved first pattern of devicefeatures and second intermediate pattern, thereby forming a secondpattern of device features corresponding to the combination of the firstand second sub-patterns, and removing the second resist layer and thetop processing layer.
 2. A method as claimed in claim 1, characterizedin that at least a third pair of a processing layer and ananti-reflection layer is added to the substrate side of the stack oflayers, and in that the following additional steps are carried out:coating the second pattern of device features with a third resist layer;transferring a third sub-pattern in the third resist layer, developingthe third resist layer, thereby forming a third intermediate patterncorresponding to the third sub-pattern; etching the third processinglayer via the second pattern of device features and the thirdintermediate pattern, thereby forming a third pattern of device featurescorresponding to the combination of the first, the second and the thirdsub-patterns; and removing the third resist layer and the secondprocessing layer.
 3. A method as claimed in claim 1, characterized inthat each sub-pattern is transferred in the corresponding resist layerby optically imaging a sub-mask, comprising the sub-pattern, in theresist layer.
 4. A method as claimed in claim 1, characterized in thatat least one of the sub-patterns is transferred to the correspondingresist layer by writing this sub-pattern in the resist layer by means ofa charged particle beam.
 5. A method as claimed in claim 3,characterized in that all sub-mask patterns are imaged with radiation ofthe same wavelength range.
 6. A method as claimed in claim 3,characterized in that at least one of the sub-mask patterns is imaged bymeans of EUV radiation and the other sub-mask patterns are imaged bymeans of DUV radiation.
 7. A method as claimed in claim 3, characterizedin that least one of the sub-mask patterns is imaged by means of acharged-particle projection beam.
 8. A method as claimed in claim 1,characterized in that, in all pairs of layers, corresponding layerscomprise the same material and have the same thickness, with theexception of the processing layer at the side of the substrate which hasa larger thickness than the other processing layer(s).
 9. A method asclaimed in claim 1, characterized in that the material of each layer ofa pair is resistant against the etching process used for etching theother layer of the pair.
 10. A method as claimed in claim 1,characterized in that the processing layers used are polysilicon layers.11. A method as claimed in claim 1, characterized in that theanti-reflection layers used are dual layers comprising ananti-reflection film and an oxide film on top of it.
 12. A method asclaimed in claim 1, characterized in that the material of a singleanti-reflection layer or the material of the end-reflection film of adual layer is an inorganic material.
 13. A method as claimed in claim12, characterized in that the inorganic material issilicon-oxide-nitride Si_(z)O_(x)N_(y).
 14. A method as claimed in claim13, characterized in that the inorganic material is silicon-nitride SiN.15. A method as claimed in claim 1, characterized in that positiveresist layers are used.
 16. A method as claimed in claim 1,characterized in that positive and negative resist layers are used. 17.A method as claimed in claim 1, characterized in that features of atleast one of the intermediate patterns are reduced in size by resistashing before etching such a pattern in the underlying processing layer.